FPGA implementation of an SD-card encryptor based on Magma cipher in counter mode

A hardware implementation of an SDSC card encryptor based on Magma cipher in counter mode is described. Implementations using two different FPGA architectures and synthesis software have similar hardware resource utilization. Keystream generation does not depend on the data which allows to increase the clock frequency of the generator. It was shown that this approach significantly reduces device operation time.