Adjusting the position of the optimum operating point of a power heterostructure field-effect transistor by forming a gate potential barrier based on a donor-acceptor structure

The first results obtained in engineering research into power heterostructure field-effect transistors operating under zero gate bias are detailed. At a frequency of 10 GHz in pulse mode under gate voltages ranging from-0.2 to +0.2 V, transistors with L-shaped gates with a length of about 0.3 $\mu$m and a width of 0.8 mm exhibited a specific power in excess of 1.6 W/mm at a gain in excess of 11 dB and a power-added efficiency of more than 40%.