Self-timed counter synthesis formalization

Self-timed (ST) circuits have high reliability. They guarantee detection and localization of any persistent faults and demonstrate a high level of fault tolerance. However, designing ST circuits is more labor-intensive compared to synchronous circuits because one should construct an additional indication subcircuit and adhere to the principles of truly ST circuit implementation. Formalized desynchronization provides automatic conversion of the original synchronous circuit description into the self-timed one but when synthesizing sequential ST units, including ST counters, it leads to excessive hardware redundancy and, as a consequence, to their low performance. The article substantiates the approach to the ST counter synthesis based on the heuristic method formalization for their construction and ensuring the guaranteed resulted truly ST implementation that functions in full accordance with the original description and has close to optimal consumer characteristics.