A new approach to implementing logical functions in field-programmable gate arrays

The expansion of the functionality of the LUT (Look up Table) logic element of field-programmable gate array (FPGA) is considered. The proposed method uses the inactive half of the element's transistor tree. The article studies a single-variable element 1-LUT implementation, which performs a logic function simultaneously with the variable decoding (DC), and its use to create an "$n$-LUT + DC FPGA." The simulation validates the item's performance and scaling to create $n$-LUT item. The analysis shows a significant gain of the proposed approach: reduced complexity in the number of transistors and reduced time delay. The developed element makes it possible to significantly increase the functionality of the logic of domestic FPGAs within the framework of existing restrictions that limit import substitution of the electronic component base.