Information Processing Letters
RUS  ENG    JOURNALS   PEOPLE   ORGANISATIONS   CONFERENCES   SEMINARS   VIDEO LIBRARY   PACKAGE AMSBIB  
Main page
About this project
Software
Classifications
Links
Terms of Use

Search papers
Search references

RSS
Current issues
Archive issues
What is RSS






Personal entry:
Login:
Password:
Save password
Enter
Forgotten password?
Register


Information Processing Letters, 2012, Volume 112, Issue 7, Pages 267–271
DOI: https://doi.org/10.1016/j.ipl.2011.12.011
(Mi ipl1)
 

This article is cited in 3 scientific papers (total in 3 papers)

Exponential lower bound for bounded depth circuits with few threshold gates

V. V. Podolskii

Steklov Mathematical Institute, Gubkina str. 8, 119991, Moscow, Russia
Full-text PDF Citations (3)
Abstract: We prove an exponential lower bound on the size of bounded depth circuits with $O(\log n)$ threshold gates computing an explicit function (namely, the parity function).
Previously exponential lower bounds were known only for circuits with one threshold gate. Superpolynomial lower bounds are known for circuits with $O(\log n)$ threshold gates.
Received: 26.05.2011
Revised: 07.12.2011
Accepted: 09.12.2011
Bibliographic databases:
Document Type: Article
Language: English
Linking options:
  • https://www.mathnet.ru/eng/ipl1
  • This publication is cited in the following 3 articles:
    Citing articles in Google Scholar: Russian citations, English citations
    Related articles in Google Scholar: Russian articles, English articles
     
      Contact us:
     Terms of Use  Registration to the website  Logotypes © Steklov Mathematical Institute RAS, 2025