Ternary sum codes for the digital circuit testing

The protection of data presented in the ternary form, are discussed. The ternary logic relevance in the future is emphasized, and the main features of the reliable digital devices development and systems are identified. A ternary sum code is described that detects any monotonous and asymmetrical errors in data vectors, the use of which is promising in the devices and systems construction with fault detection. The constructing principles a ternary sum code is similar to the constructing principles classical binary sum codes (Berger codes). The previously unknown ternary sum codes properties in the event of errors only in data vectors with error-free check bits are established. Such a task is relevant in practical applications in which the check bits and data vectors are calculated by physically different devices. Taking into account the established ternary sum codes properties can be useful when choosing a method of protecting both the data itself and parrying faults arising in automation devices.