Comparative assessment of III–V heterostructure and silicon underlap double gate MOSFETs

Comparative assessment of III–V heterostructure and silicon underlap DG-MOSFETs, is done using 2D Sentaurus TCAD simulation. III–V heterostructure device has narrow-band In$_{0.53}$Ga$_{0.47}$As and wide-band InP layers for body, and high-$K$ gate dielectric. Density gradient model is used for simulation and interface traps are considered. Benchmarking of simulation results show that III–V device provides higher on current, lesser delay, lower energy-delay product and lower DIBL than silicon device. However III–V device has higher SS and lower Ion/Ioff than silicon device. The results indicate that there is a need to optimize the $I_{\mathrm{on}}/I_{\mathrm{off}}$, SS and DIBL values for specific circuits.