Quantum corrections to threshold voltages for fully depleted SOI transistors with two independent gates

The linear charge coupling effect of threshold voltages $V_{\mathrm{th}}$ of the bottom (field) gate, i.e., a substrate of the silicon-on-insulator structure of fully depleted $n$-MIC transistors on a lightly doped silicon layer 20–50 nm thick, is studied depending on the voltage $V_{\mathrm{bg}}$ of the top asymmetrically biased (with negative polarity) $N^+$-poly-Si gate. It is shown that the quantum-mechanical correction conditioned by the electrostatically induced size effect of the transverse field should be considered when determining the linear charge coupling region between gates even at a silicon layer thickness of $\sim$ 50 nm. An increase in the positive charge on the surface states at the heterointerface with a silicon layer increases the quantum-mechanical correction by a factor of 2–4 due to the quantum capacitance effect affecting donor-trap recharging in the case of a significant difference between the opposite-polarity potentials of the two gates.